Machine Level Instructions (in the General Model)

Instruction Components

• Operation Code

  • The first element of a machine level instruction is almost always a fixed length collection of bits containing a code that identifies the specific operation to be performed
  
  
  • While not all possible bit patterns that could appear in this operation code (or op code) field need necessarily be valid operation identifiers, the number of possible bit patterns provides an upper limit for the number of operations that the processor could support. For example, an 8-bit op code would limit a processor to a maximum of 256 different operations.
    
  
  

  • Operands

    - generally speaking, most modern processors are limited at the machine level to instructions with no more than two operands; however, these operands may take several different forms:
    • Register Identifier - Most processors contain several internal, general purpose registers. Selection of a specific register from among those possible requires that the register be identified within the instruction. Each register requires its own unique code. The maximum number of such registers is therefore limited by the length of a register identification field within the instruction.
      
    • Immediate Values - In some processors, some instructions may carry the actual value to be used by the instruction as part of the instruction; for example, at the machine level, an 80x86 processor accepts the equivalent of an instruction "ADD AX,25" to add 25 to the value in a specified register (called AX in this case), where the value 25 is part of the instruction, instead of a value stored in memory somewhere else and pointed to by an "address operand".
      
    • Addresses
      • Direct Addresses - the actual numeric address of a memory location of a data value to be used is contained in the instruction; for example, at machine level, an 80x86 processor accepts the equivalent of an instruction "ADD AX,[25]" where "[25]" means the number found in memory at memory address 25 (and not the number 25 itself).
      • Indirect Addresses - instead of having an actual address contained within the instruction, a register identification code may be supplied which identifies a register which contains an address of a memory location which contains the value to be used by the instruction; again, for example, the 80x86 accepts, at the machine level, the equivalent of an instruction "ADD AX,[BX]" where BX is a register which contains the address of a memory location, which in turn contains the actual data value to be used; by modifying the value in the register (BX in this case) the same instruction can be used to add values to the "accumulating register" (AX in this case) from different memory locations (for example from the entries in a table of values).
      • Indexed/Based Addressing - direct and indirect addressing can be combined within a single instruction, so that the actual address being used is the sum of a "direct value" specified in the instruction plus the contents of some register. There are two basic ways to think about this: the "direct address" portion can be thought of as the beginning address of a list or table with the register providing an "index" or distance from the beginning of the table to the desired data value; or alternately, the register can be thought of as being set-up with a "base address" location (typically for a routine) and the "direct address" portion supplies a "displacement" or "offset" (from the beginning of the routine) to the desired location. In many processors, both concepts can be combined in a single instruction, so that the instruction contains a "direct address" value, plus an "index register" ID, plus a "base register" ID (and all three need to be added together to get the "real" address of the data value to be used.
    
    
    
    
    

    Fixed vs. Variable Length Instructions

    • Multiple Instruction Formats

      - A (hopefully) obvious side effect of having so much flexibility in the types of operands possible, is the fact that (generally speaking) different instruction formats will be required depending upon the specific types of operands employed for individual instructions.

    
    
    
    • Incrementing the Program Counter

      - Allowing for multiple instruction formats almost always results in different instructions requiring different amounts of memory to store them (it should take less space to hold an instruction with only 1 register ID code than to hold a different instruction with 2 or 3 register ID codes plus a "direct address". As part of the instruction cycle, the Control Unit, once the instruction has been retrieved from memory, must increment the Program Counter to point to the physically next instruction. How much the Control Unit must increment the Program Counter by depends upon the specific instruction just retrieved (or more correctly, upon the length of the specific instruction just retrieved) from memory. This means that the Control Unit will need to examine the op code field to determine the type of instruction and from that information determine the instruction length. This indirectly also means that two instructions which are superficially doing the same operation but which have different operand structures (such as "ADD AX,[BX]" and "ADD AX,[25+BX]") must have different op code patterns.

    
    
    
    
    

    Example: IBM/360 Instruction Formats

    All instructions have an 8-bit (1-byte) op code

    • RR-type Format

      - the op code is followed by two 4-bit register ID codes, resulting in a 2-byte instruction length. A typical RR instruction would be SR (subtract register) which subtracts the value in the second register specified from the value in the first register specified.
    
    
    

    • RX-type Format

      - the op code is followed by a 4-bit register ID operand plus an indeXed-type address; an indeXed address is composed of a 12-bit "direct address", plus a 4-bit "index register" ID, plus a 4-bit "base register" ID; this results in a total instruction length of 4 bytes. A typical RX-type instruction would be A (add) which adds the contents of memory at an "indexed address" to a specified register.
    
    
    

    • RRS-type Format

      - (more commonly called RS-type) this is one of the rare exceptions to the "maximum of 2 operands per instruction" rule; the op code is followed by two 4-bit register ID operands plus a Storage-type address third operand; a Storage-type address is composed of a 12-bit "direct address" plus a 4-bit "base register" ID (but no "index register"); total instruction length is again 4 bytes. A typical RRS instruction would be STM (store multiple) which stores the contents of all registers within a specified range (the two register ID values supply the range) into memory starting at the specified Storage address.
    
    
    

    • SI-type Format

      - the op code is followed by a single byte "immediate" data value plus a Storage-type address (as above) for a total instruction length of 4 bytes. A typical SI instruction would be SI (store immediate) which stores a copy of the byte value supplied (possibly an EBCDIC character code) into a byte at the specified Storage location.
    
    
    

    • SS-type1 Format

      - the op code is followed by a 1 byte "immediate" value for a length plus two Storage-type addresses for a total length of 6 bytes. Because the length is a 1 byte field, lengths for such instructions are limited to a maximum of 256 bytes. A typical SS-type1 instruction would be MVS (move string) used to "move" or copy a string (of from 1 to 256 bytes) from one Storage address to another.
    
    
    

    • SS-type2 Format

      - this is almost identical to the SS-type1 except that two 4-bit lengths are included, one for each of the Storage-type addresses. Because each length is only a 4-bit field, SS-type2 lengths are limited to 16 bytes. A typical SS-type2 instruction would be PACK which converts a zoned decimal value of a specified length at some Storage location into a packed decimal value of a (possibly different) length at some other Storage location.

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