Input and Output - Port IO
Device input and/or output may be handled in a manner very much like memory loads and stores.
The difference, from the processor perspective, is only in terms of some minor Control sub-bus
activity (and a much longer access delay). External devices must have enough built-in intelligence
to know how to respond appropriately to the bus signals they receive.
The External Bus Elements
Data Sub-Bus
- carries actual data values to and from the processor from and to memory and input/output
devices.
Address Sub-Bus
- carries the address of the memory cell or I/O device with which the processor is trying to
communicate.
Control Sub-Bus
- carries timing signals and signals indicating the specific operation being attempted e.g.
"Memory Enable" and "Read/Write" for load and store operations./li
Processor-Side Output Actions
Each device is assigned a "port" address number; the processor outputs to a device using its port
address, much the same as if it were attempting to store the data in memory.
Data Sub-Bus
- the actual data value to be output.
Address Sub-Bus
- the port address of the device.
Control Sub-Bus
- "Device Enable" (instead of the "Memory Enable" used to "store") and the Write setting of the
"Read/Write" signal.
Comparison with Memory Store
- the port address is indistinguishable from a memory address, so, from the processor's point of
view, the only difference between Port Output and Memory Store is in the use of a "Device
Enable" instead of a "Memory Enable" signal.
Processor-Side Input Actions
Address Sub-Bus
- the port address of the input device.
Control Sub-Bus
- "Device Enable" and the Read setting of the "Read/Write" signal.
Data Sub-Bus
- the data value coming back from the input device to the processor.
Comparison with Memory Load
- from the processor's perspective, the only difference between Port Input and Memory Load
(other than the fact that device input takes much longer) is in the use of the "Device Enable"
instead of the "Memory Enable" signal.
Device Input/Output Response
Control Sub-Bus
- the "Device Enable" signal "wakes up" the device and indicates that the device should examine
the Address sub-bus.
Address Sub-Bus
- the device compares the value on the Address sub-bus with its own port address; if the
addresses do not match the device "goes back to sleep".
Data Sub-Bus
- when the device's port address matches the Address sub-bus, then the device knows that this is
an I/O request for itself (and not some other device), so, depending upon the type of request, it
either takes the data value off the Data sub-bus (an Output request) or sets a data value on the
Data sub-bus (an Input request).